One of the promising dual channel CMOS (complementary metal-oxide-semiconductor) integrations schemes for current and future technology nodes is to utilize tensile-strained silicon (Si) channels for n-type FET (field effect transistor) devices and to utilize compressively-strained silicon-germanium (SiGe) channels for p-type FET devices. The use of SiGe channels for p-type MOSFET devices is known to enhance the carrier (hole) mobility as compared to Si alone. For CMOS technologies, silicon dioxide (SiO2) has traditionally been used as the gate dielectric for MOSFET devices. As the dimensions of MOSFET devices continue to shrink, however, the thickness of the SiO2 gate dielectric layer must also decrease to maintain the requisite capacitance between the control gate and channel. However, the scaling of SiO2 gate dielectric layers (e.g., 2 nm or less) poses problems in that leakage current through the gate dielectric increases exponentially with the decrease in the thickness of the gate dielectric. As such, high-k gate dielectrics have been utilized in place of Sift to enable thicker gate dielectric layers to reduce leakage, while allowing scaling down of the EOT (equivalent oxide thickness) of the gate dielectric.
The use of high-k gate dielectric materials is problematic in that such dielectric materials typically do not interface well with silicon layers. For example, high-k gate dielectric materials do not passivate a silicon surface, which results in a large number of interface traps and charges and other issues which can degrade device performance. As such, high-k dielectric gate materials are often used in conjunction with a thin interfacial silicon oxide layer which provides an interface between the silicon channel layer and the high-k gate dielectric layer. However, the optimization of a silicon oxide interfacial layer between a high-k dielectric layer and a SiGe channel layer is non-trivial due to the complexity arising from the coexistence of Si and Ge interfacial oxides.
For example, SiGe channel FETs are known to have a high interface trap charge (Nit) at the interface between the interfacial layer and the surface of the SiGe channel layer, which might be attributed to undesired formation of germanium oxide (GeOx). The resulting mixed SiOx/GeOx interface causes large interface trap densities due to distorted Ge—O bonds across the interface. While nitridation of the silicon oxide layer is known to be effective to suppress GeOx formation, the nitridation of silicon oxide is also problematic in that the nitridation of the silicon oxide causes an increase in the interface trap charge density and mobility degradation. The presence of defective high-k/SiGe interfaces limits the performance of SiGe-channel FET devices.